1. Field of the Invention
The invention relates in general to a memory and a manufacturing method thereof, and more particularly to a memory having a number of bit lines and a number of word lines crossed with but not perpendicular to the bit lines and a manufacturing method thereof.
2. Description of the Related Art
Referring to FIGS. 1A˜1B. FIG. 1A is a partial top view of a conventional dual bit nitride read only memory. FIG. 1B is a cross-sectional view of a dual bit nitride read only memory (NROM) along the cross-sectional line 1B˜1B′ of FIG. 1A. In FIGS. 1A˜1B, the NROM 100 includes a silicon substrate 105, a number of embedded bit lines 110, a number of word lines 120, a number of oxide-nitride-oxide (ONO) structures 130b, a number of barrier diffusion oxide layers 140, a number of memory cells 130a (enclosed in larger dotted circles in FIG. 1A and FIG. 1B), a number of first bit storage nodes 133 and a number of second bit storage nodes 135 (enclosed in smaller dotted circles in FIG. 1A and FIG. 1B).
The embedded bit lines 110 are disposed in parallel and formed in the silicon substrate 105. The word lines 120 are disposed in parallel and formed on the silicon substrate 105. The work line 120 are vertically criss-crossed with the embedded bit line 110. The ONO structures 130b are disposed between each word line 120 and the silicon substrate 105. Each ONO structure 130b includes a bottom oxide layer 137, a silicon nitride (SiN) layer 138 and a top oxide layer 139 in a bottom-up order. Besides, the barrier diffusion oxide layers 140 are formed on the embedded bit lines 110 for isolating the word lines 120 and the bit lines. The first bit storage node 133 and the second bit storage node 135 are correspondingly formed in each ONO structure 130b adjacent to the two barrier diffusion oxide layers 140.
Since the NROM 100 are normally exposed to background radiation, the electron concentration in the first bit storage node 133 and the second bit storage node 135 of the memory cell 130a tends to decrease. Consequently, errors may occur to the bits stored in the memory cell, affecting the correctness of the overall data when reading.